Product Summary

The SST27SF512-70-3C-PGE is a 64K ×8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high perfor-mance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST27SF512-70-3C-PGE can be electrically erased and pro-grammed at least 1000 times using an external program-mer with a 12V power supply. The device has to be erased prior to programming. The device conforms to JEDEC stan-dard pinouts for byte-wide memories.

Parametrics

SST27SF512-70-3C-PGE absolute maximum ratings: (1)Temperature Under Bias: -55℃ to +125℃; (2)Storage Temperature: -65℃ to +150℃; (3)D. C. Voltage on Any Pin to Ground Potential: -0.5V to VDD +0.5V; (4)Transient Voltage (<20 ns) on Any Pin to Ground Potential: -2.0V to VDD +2.0V; (5)Voltage on A9and VPPPin to Ground Potential: -0.5V to 14.0V; (6)Package Power Dissipation Capability (TA= 25℃): 1.0W; (7)Through Hole Lead Soldering Temperature (10 Seconds): 300℃; (8)Surface Mount Solder Reflow Temperature1: 260℃ for 10 seconds; (9)Output Short Circuit Current: 100 mA.

Features

SST27SF512-70-3C-PGE features: (1)Organized as 64K x8 / 128K x8 / 256K x8; (2)4.5-5.5V Read Operation; (3)Superior Reliability, Endurance: At least 1000 Cycles; Greater than 100 years Data Retention; (4)Low Power Consumption, Active Current: 20 mA (typical); Standby Current: 10 μA (typical); (5)Fast Read Access Time, 70 ns; (6)Fast Byte-Program Operation, Byte-Program Time: 20 μs (typical) Chip Program Time: 1.4 seconds (typical); (7)Electrical Erase Using Programmer, Does not require UV source; Chip-Erase Time: 100 ms (typical); (8)TTL I/O Compatibility; (9)JEDEC Standard Byte-wide EPROM Pinouts; (10)Packages Available, 28-pin PDIP; (11)All non-Pb (lead-free) devices are RoHS compliant.

Diagrams

SST27SF512-70-3C-PGE block diagram

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SST27SF512-70-3C-PGE
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